module running_disparity(rd_temp,rd_common,in12b,out_common);
input rd_temp;
input [11:0] in12b;
output [9:0] out_common;
output rd_common;
wire rd_temp;
wire [11:0] in12b;
reg [9:0] out_common;
reg rd_common;

always@(in12b or rd_temp)begin
case({in12b[11],in12b[6],rd_temp})
	3'b000: begin 	out_common <= {	in12b[5:0]	,	in12b[10:7]	} ; rd_common <= rd_temp ; 	end
	3'b001: 
	begin
 	out_common <= (in12b[5:0]==111000)?{~in12b[5:0],in12b[10:7]}:{in12b[5:0],in12b[10:7]} ; 
	rd_common <= rd_temp ; 	
	end
	3'b010: begin 	out_common <= {	in12b[5:0]	,	in12b[10:7]	} ; 	rd_common <= ~rd_temp ; 	end
	3'b011: begin 	out_common <= {	~in12b[5:0]	,	in12b[10:7]	} ; 	rd_common <= ~rd_temp ; 	end
	3'b100: begin 	out_common <= {	in12b[5:0]	,	in12b[10:7]	} ; rd_common <= ~rd_temp ; 	end
	3'b101: 
	begin 	
	out_common <= (in12b[5:0]==111000)?{~in12b[5:0],~in12b[10:7]}:{	in12b[5:0],~in12b[10:7]} ; 
	rd_common <= ~rd_temp ; 	
	end
	3'b110: begin 	out_common <= {	in12b[5:0]	,	~in12b[10:7]	} ; rd_common <= ~rd_temp ; 	end
	3'b111: begin 	out_common <= {	~in12b[5:0]	,	in12b[10:7]	} ; rd_common <= ~rd_temp ; 	end
endcase
end
endmodule

